The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a nonvolatile memory device in which a dummy conductive pattern is formed on a field oxide film between a cell array region and a peripheral circuit region and to a manufacturing method thereof.
A flash EEPROM has a floating gate for storing data and a control gate for controlling the floating gate, and is characterized by data being programmed or erased by application of a high voltage signal to the control gate or a pocket well.
The technique of the flash EEPROM is disclosed in detail in "A 2.3 .mu.m.sup.2 Memory Cell Structure for 16 Mb NAND EEPROMs" of pp. 103-106 of IEDM written by R. Shirota et al in 1990.
In manufacturing the flash EEPROM, a self alignment process in which accumulated multilayer materials are simultaneously etched is necessary for forming the control gate and the floating gate.
FIGS. 1A through 1C are sectional views for illustrating a conventional manufacturing method of a nonvolatile memory device, particularly, the above-mentioned self alignment process.
First, field oxide film 4 is formed on a surface of semiconductor substrate 2, and thin oxide film 6 is formed on an active region of the semiconductor substrate, and then floating gate formation material 8 and insulating film 10 are accumulated. Subsequently, floating gate formation material 8 and insulating film 10 are etched using a mask pattern (not shown) for forming a floating gate, and then control gate formation material 12 is deposited on the whole surface of the resultant substrate. Next, first photosensitive film pattern 16 covering a cell array region and gate electrodes of a peripheral circuit region is formed (see FIG. 1A).
Through an etching process, using the first photosensitive film pattern 16, control gate pattern 12a is formed in the cell array region, and gate electrode 12b is formed in the peripheral circuit region. Then, second photosensitive film pattern 17, for covering the peripheral circuit region and the region where a control gate of the cell array region will be formed, is formed (see FIG. 1B).
By simultaneously etching of the accumulated materials, using the second photosensitive film patterns for forming the control gate as a mask (the process of self alignment), cells having floating gate 8a, insulating film 10 and control gate 12c are formed in the cell array region (see FIG. 1C).
While the distance between cells becomes narrower, as integration of the memory device is increased, the thickness of accumulated layers on the semiconductor substrate such as the floating gate formation material, the insulating film, the control gate formation material and the second photosensitive film pattern remains unchanged. Accordingly, the aspect ratio(height/width) between the patterns becomes higher during the process of self alignment (the processes of FIGS. 1B and 1C).
The distance between the cells (reference character "A" of FIG. 1B) is reduced to about 0.5 .mu.m as integration is increased, while the height of a cell pattern including the floating gate, the control gate and the second photosensitive film pattern is approximately 1.5 .mu.m. Accordingly, a very high aspect ratio of approximately 3.0 results during the process of self alignment. The usual thickness of the floating gate is 1,000 .ANG.-2,000 .ANG., that of the control gate is approximately 3,000 .ANG., and that of the second photosensitive film pattern is approximately 10,000 .ANG..
In the case of a high aspect ratio between patterns, etchant flows between the patterns so unstably that the patterns form non-uniformly.
FIGS. 2A through 2D are sectional views for illustrating another conventional manufacturing method of a nonvolatile memory device, which is proposed for solving the problems described above and illustrated in FIGS. 1A through 1C.
An insulating material layer is coated on the control gate formation material, and then first photosensitive film pattern 16 is formed the such manner as that described above with respect to FIG. 1A. Subsequently, the accumulated materials on the semiconductor substrate are etched using first photosensitive film pattern 16 to form gate electrode 12b in the peripheral circuit region 16, and pattern 12a for forming a control gate in the cell array region (see FIG. 2A). Here, insulating material patterns 15a and 15b are formed on pattern 12a for forming the control gate and gate electrode 12b, respectively.
Subsequently, second photosensitive film pattern 17 is formed on the resultant substrate having insulating material patterns 15a and 15b, and then control gate pattern 15c is formed by anisotropically etching insulating material patterns 15a and 15b using second photosensitive film pattern 17 as a mask (see FIG. 2B). The second photosensitive film pattern 17 is then eliminated (see FIG. 2C).
Through an anisotropic etching process using control gate pattern 15c as a mask, cells having floating gate 8a, insulating film 10 and control gate 12c are formed in the cell array region (see FIG. 2D).
In the manufacturing method as described in FIGS. 2A through 2D, the process of self alignment is performed using insulating material patterns 15a and 15b as a mask, so that the aspect ratio between patterns can be lowered by the height of the second photosensitive film pattern. Accordingly, non-uniformity of patterns due to non-uniform flow of etchant running between patterns can be reduced.
However, damages "D" to substrates occur in the peripheral circuit region and the boundary region, as shown in FIG. 2D, causing deterioration in the reliability of the memory device.